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Lecture 01 - RISC-V Basics

Lecture 01 - RISC-V Basics

Course: Computer Architectures

Topics

What to remember from this lecture

RISC-V instructions use fixed operand formats. Registers hold full machine-word values, while immediates are constants encoded directly inside instructions.

Useful register facts:

x0 = always 0
x1 = ra
x2 = sp

The ABI names such as ra and sp are aliases for numbered registers.

Immediate instructions

addi rd, rs1, imm

means:

rd = rs1 + imm

For addi, the immediate is signed and 12 bits wide.

Small constants can therefore be loaded with:

addi rd, x0, imm

The pseudo-instruction:

li rd, value

lets the assembler choose the real instruction sequence needed.

For larger values, this may require lui and addi.

lui

lui rd, imm20

places the immediate in bits 31:12 and makes the lower 12 bits zero.

Example:

lui x5, 0x12345

produces:

0x12345000

Signed lower-immediate issue

A 12-bit immediate with bit pattern 0x800 represents -2048.

Therefore loading 0x1800 can use:

lui  x5, 0x2
addi x5, x5, -0x800

because:

0x2000 - 0x0800 = 0x1800

ALU instructions covered

Shift left

sll  x3, x2, x1
slli x3, x2, 4
  • sll: shift amount comes from a register.
  • slli: shift amount is an immediate.

Set less than immediate

slti x3, x2, 4

sets x3 to 1 if x2 < 4, otherwise 0.

Zero tests

seqz x3, x2
snez x3, x2
  • seqz: set to 1 if source is zero.
  • snez: set to 1 if source is nonzero.

Branch basics

Branches are conditional jumps.

Common instructions:

beq   equal
bne   not equal
blt   signed less-than
bge   signed greater-or-equal
bltu  unsigned less-than
bgeu  unsigned greater-or-equal

Signed and unsigned comparisons use the same register bits but interpret them differently.

Questions to review

  • Why is the immediate in addi restricted?
  • Why can 0x800 mean -2048?
  • Why can li expand to multiple instructions?
  • What changes between blt and bltu?

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