MIPS R4000 Pipeline
The lecture’s R4000 example divides instruction and data memory access across more stages to support a higher clock frequency.
Lecture framing
The professor introduces the MIPS R-4000 as a 64-bit microprocessor introduced in 1991, with an instruction set similar to MIPS64. Its eight-stage pipeline accommodates slower cache access and a higher clock frequency. The lecture calls such long pipelines superpipelines.
Eight stages
IF -> IS -> RF -> EX -> DF -> DS -> TC -> WB
| Stage | Role as presented on the slides |
|---|---|
| IF | First part of instruction fetch |
| IS | Second part of instruction fetch |
| RF | Instruction decode, register fetch, hazard checking |
| EX | Effective address calculation, ALU operation, branch target computation, condition evaluation |
| DF | First part of data fetch |
| DS | Second part of data fetch |
| TC | Last part of data fetch |
| WB | Write-back for loads and register-register operations |
These descriptions retain the professor’s framing, including TC as the last part of data fetch.
Both instruction and data memory accesses are pipelined. A new instruction can start every cycle when hazards permit; eight stages do not imply one new instruction every eight cycles.
Consequences of the deeper pipeline
- More forwarding paths are required.
- Load delay slot increases to 2 cycles in the shown timing.
- Branch delay slot increases to 3 cycles in the shown timing.
The load example forwards data from the end of DS. Branch condition evaluation occurs in EX. See Load and Branch Delay Slots for the cycle-by-cycle reasoning and the scope of the lecture’s delay-slot terminology.
Keep the two pipeline examples separate
The earlier IF-ID-EX-MEM-WB extension illustrates multicycle hazards using A1...A4 and M1...M7. The R4000 has different integer stages and its own FP stage types and timings: MIPS R4000 FP Pipeline.
Related: Multicycle Operations, Pipeline CPI and Stall Costs.
Source
E. Sanchez, Multicycle operations, Politecnico di Torino, ASE 2026/27, slides 21-35. PDF page numbers match slide numbers.
Lecture context: Lecture 05 - Multicycle Operations. Sections marked as clarification or reusable explanation add study guidance to the slide material.