Load and Branch Delay Slots
Pipeline delays arise because a value or branch decision becomes available after younger instructions have already entered the pipeline.
This note follows the professor’s R4000 timing and terms: load delay slot (2 cycles) and branch delay slot (3 cycles).
Load delay: waiting for data
In slides 32-33, a load starts in cycle 1, executes in cycle 4, and has data available at the end of DS in cycle 6. The consumer can use forwarded data in EX in cycle 7.
| Instruction | IF cycle | EX cycle | Meaning |
|---|---|---|---|
| Load | 1 | 4 | Data becomes available at end of DS, cycle 6 |
| Instruction 1 | 2 | 5 | Cannot yet use the loaded value in EX |
| Instruction 2 | 3 | 6 | Cannot yet use the loaded value in EX |
Dependent ADDD | 4 | 7 | Can use the forwarded value |
The two positions between load and consumer can contain safe independent instructions. If a dependent instruction follows immediately, it must wait for equivalent timing. Forwarding avoids waiting until WB, but cannot remove the wait before DS produces the data.
Branch delay: waiting for the decision
In slides 34-35, the branch starts in cycle 1 and evaluates its condition in EX in cycle 4. The target starts fetching in cycle 5.
Meanwhile three sequential instructions have begun fetching in cycles 2, 3, and 4. The diagram labels this three-cycle window BRANCH DELAY SLOT.
Clarification of terminology
The lecture uses “delay slot” to describe the illustrated timing windows. A timing window alone does not specify which younger instructions must architecturally execute, which are discarded, or what branch prediction policy is used. Do not infer three architecturally mandatory branch-delay instructions solely from this diagram.
Common mistake
Load delay concerns a RAW dependency on data. Branch delay concerns control flow. Their cause and safe scheduling rules are different, even though both add bubbles when useful work cannot fill the gap.
Related: MIPS R4000 Pipeline, Latency and Initiation Interval, Pipeline CPI and Stall Costs.
Source
E. Sanchez, Multicycle operations, Politecnico di Torino, ASE 2026/27, slides 31-35. PDF page numbers match slide numbers.
Lecture context: Lecture 05 - Multicycle Operations. Sections marked as clarification or reusable explanation add study guidance to the slide material.