Structural Hazards in Multicycle Pipelines
A structural hazard occurs when instructions need more of a hardware resource than is available at the required time.
Divider occupancy
The introductory divider is unpipelined. A second divide cannot start while the unit cannot accept it. Its initiation interval is 25 cycles, even if the two divides are completely independent.
This is a resource conflict, not a dependency between their register values.
Simultaneous register writes
Different execution paths can converge on WB in the same cycle. The professor calls this contemporary register writes.
Slide 12 shows:
| Instruction | IF cycle | Execution path | WB cycle |
|---|---|---|---|
fmul.d f0,f4,f6 | 1 | M1...M7 | 11 |
fadd.d f2,f4,f6 | 4 | A1...A4 | 11 |
fld f2,0(x2) | 7 | EX | 11 |
With one write port, all three writes cannot occur together. The add/load destination overlap also needs the separate WAW check; a write-port stall alone does not define correct write order.
Lecture solutions
- Add more write ports, which the professor describes as normally too expensive.
- Stall instructions in ID.
- Alternatively, stall before entering MEM or WB.
Clarification: checking a future conflict
For fixed execution times, ID can reason about the cycle in which a newly issued instruction will need WB. Checking only whether the write port is busy now would miss a collision several cycles later. This explains why issue-time hazard detection must consider future resource use.
Related: Multicycle Operations, Latency and Initiation Interval, RAW and WAW Hazards, Hazard Detection in ID.
Source
E. Sanchez, Multicycle operations, Politecnico di Torino, ASE 2026/27, slides 6-8, 11-13, 20. PDF page numbers match slide numbers.
Lecture context: Lecture 05 - Multicycle Operations. Sections marked as clarification or reusable explanation add study guidance to the slide material.