RAW and WAW Hazards

RAW protects the value a reader receives. WAW protects the order in which writers update a destination.

RAW: Read After Write

A younger instruction needs a register value produced by an older instruction. A dependency becomes a timing hazard when that value is unavailable at the stage where it is needed.

The professor’s example chain is:

fld    f4, 0(x2)
fmul.d f0, f4, f6
fadd.d f2, f0, f8
fsd    f2, 0(x2)

The multiply needs the load’s f4; the add needs the multiply’s f0; the store needs the add’s f2. Longer execution paths extend the stalls. Forwarding helps after a result becomes available, but cannot produce it early.

The operand-use stage matters: the store’s address is needed in EX, while its data is needed in MEM in the introductory diagram. Waiting for store data need not stop its address calculation.

WAW: Write After Write

Two instructions write the same register. The final architectural value must come from the younger instruction.

The lecture highlights these writers, with other instructions between them:

fadd.d f2, f4, f6   # older writer
# intervening instructions
fld    f2, 0(x2)    # younger writer

If the younger load writes first and the older add writes later, the final f2 is wrong. Unequal execution lengths create this risk. The shown timing also brings writes together, so write-port availability must be checked separately.

The professor’s solution is to check the new destination against older instructions still executing and stall the new instruction on a match.

Compare the hazards

Hazard	Matching items	Required protection
RAW	Younger source = older destination	Reader gets the correct, ready result
WAW	Younger destination = older destination	Final value comes from younger writer
Structural write conflict	Two writes need the same port in one cycle	Hardware serves no more writes than it supports

Two different destination registers can still compete for one write port. Two writes to the same register can violate write order even in different cycles.

Related: Hazard Detection in ID, Structural Hazards in Multicycle Pipelines, Latency and Initiation Interval.

Source

E. Sanchez, Multicycle operations, Politecnico di Torino, ASE 2026/27, slides 10, 14-20. PDF page numbers match slide numbers.

Lecture context: Lecture 05 - Multicycle Operations. Sections marked as clarification or reusable explanation add study guidance to the slide material.